Study of the Reliability for the Leakage Mitigation Methods using FinFETs

Introduction: In the very large-scale integration (VLSI) industry, scaling plays an important role in providing compact size and high-speed digital circuits. The major drawbacks faced by logic circuits are power dissipation and process, voltage, and temperature (PVT) variations. In the VLSI industry, the prediction of variability tolerance capability is mandatory to know the future performance of the circuits. The impact of PVT variation is large in nanoscale logic circuits and it has the power to alter the output characteristics of any logic circuit. The reasons that cause PVT variations are manufacturing defects, environmental conditions, and mishandling issues. Aims and Objective: This paper aims to discuss the process variations and briefly describe the previous work related to variability and various factors involved in PVT simulations. It also provides the idea of Monte-Carlo simulation in the Cadence Virtuoso tool. Methods: In this paper, the impact of PVT variations on different fin-shaped field effect transistor (FinFET) circuits was evaluated using the Cadence Virtuoso tool. Monte-Carlo simulation was performed on various leakage reduction techniques for the domino logic with the help of a multi-gate predictive technology model (PTM) FinFET at a 16nm technology node. Results: The footer-less domino logic (FLDL) circuit is designed and simulated using different leakage reduction techniques for reliability analysis. Conclusion: Cascaded leakage control transistor (CLCT) approach shows 81.75%, 67.83%, and 51.25% less statistical mean value for power dissipation as compared to conventional, on-off logic (ONOFIC), and alternative ONOFIC approaches in the case of FLDL OR2 logic circuit, respectively.